成员变量
__IOM uint32_t	CR1

__IOM uint32_t	CR2

__IOM uint32_t	SMCR

__IOM uint32_t	DIER

__IOM uint32_t	SR

__IOM uint32_t	EGR

__IOM uint32_t	CCMR1

__IOM uint32_t	CCMR2

__IOM uint32_t	CCER

__IOM uint32_t	CNT

__IOM uint32_t	PSC

__IOM uint32_t	ARR

__IOM uint32_t	RCR

__IOM uint32_t	CCR1

__IOM uint32_t	CCR2

__IOM uint32_t	CCR3

__IOM uint32_t	CCR4

__IOM uint32_t	BDTR

结构体成员变量说明

◆ ARR

__IOM uint32_t ARR

TIM auto load register, Address offset: 0x02C

◆ BDTR

__IOM uint32_t BDTR

TIM brush and dead register, Address offset: 0x044

◆ CCER

__IOM uint32_t CCER

TIM captuer/compare enable register, Address offset: 0x020

◆ CCMR1

__IOM uint32_t CCMR1

TIM capture/compare mode register 1, Address offset: 0x018

◆ CCMR2

__IOM uint32_t CCMR2

TIM capture/compare mode register 2, Address offset: 0x01C

◆ CCR1

__IOM uint32_t CCR1

TIM captuer/compare register 1, Address offset: 0x034

◆ CCR2

__IOM uint32_t CCR2

TIM capture/compare register 2, Address offset: 0x038

◆ CCR3

__IOM uint32_t CCR3

TIM capture/compare register 3, Address offset: 0x03C

◆ CCR4

__IOM uint32_t CCR4

TIM capture/compare register 4, Address offset: 0x040

◆ CNT

__IOM uint32_t CNT

TIM count register, Address offset: 0x024

◆ CR1

__IOM uint32_t CR1

TIM control register 1, Address offset: 0x000

◆ CR2

__IOM uint32_t CR2

TIM control register 2, Address offset: 0x004

◆ DIER

__IOM uint32_t DIER

TIM interrupt enable register, Address offset: 0x00C

◆ EGR

__IOM uint32_t EGR

TIM event trig register, Address offset: 0x014

◆ PSC

__IOM uint32_t PSC

TIM prescale register, Address offset: 0x028

◆ RCR

__IOM uint32_t RCR

TIM repeate count register, Address offset: 0x030

◆ SMCR

__IOM uint32_t SMCR

TIM slave mode control register, Address offset: 0x008

◆ SR

__IOM uint32_t SR

TIM status register, Address offset: 0x010

该结构体的文档由以下文件生成:

wb32l003.h